The present invention relates in general to forming semiconductor devices for use in integrated circuits (ICs). More specifically, the present invention relates to improved fabrication methodologies and resulting structures for semiconductor devices (e.g., vertical field effect transistors (FETs)) that include relatively high aspect ratio gate structures.
Semiconductor devices are typically formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an IC having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material.
One type of MOSFET is a non-planar FET known generally as a vertical FET. In order to decrease gate pitch (i.e., the center-to-center distance between adjacent gate features/structures) and increase device density on the wafer, the aspect ratios of the channel region and the gate region of a typical vertical FET device are high. In other words, the channel and gate regions are each much taller than they are wide.